Welcome to ETS 2027
We’re thrilled to welcome you to the 32nd Edition of ETS, the 32nd IEEE European Test Symposium (ETS2027). The conference includes scientific papers, industrial contributions, student activities, special sessions, panels, embedded tutorials and fringe workshops.
Scientific Papers
Research contributions and emerging technical directions.
Industrial Contributions
Industrial case studies, vendor sessions and applied results.
Student Activities
PhD Forum, McCluskey Thesis Contest and student-focused sessions.
Conference Topics
T8 – Test Generation, Fault Modeling & Simulation, Diagnosis
Test generation, fault modeling/fault simulation and diagnosis techniques across various abstraction levels, e.g. cell-aware, gate-level, system-level, as well as for different fault models, e.g. traditional, defect-oriented and transient. Sub-topics include: adaptive testing; ATPG; defect-oriented testing; fault simulation; transient faults; system-level test; solving techniques; delay test; efficiency/effectiveness; feedback & iterative improvement; pre- and post-silicon diagnosis.
T7 – Validation, Verification, and Debug
Methodologies and tools for validation, verification and debug of ICs, embedded hardware and software, and cyber-physical systems, by exploiting formal, semi-formal and dynamic approaches, with or without the use of artificial intelligence. Topics include: testbench and assertion generation and qualification; fault/mutant modeling and simulation; checker synthesis and optimization; multi-domain and mixed-critical validation and verification techniques; pre- and post-silicon debugging solutions; security verification and detection of vulnerabilities; formal verification methods and core algorithm techniques supporting formal verification; acceleration-driven and emulation-based approaches for verification; verification and validation of safety mechanisms.
T6 – DFT, Test Access Standards and Test Application
Design for Testability (DFT) solutions are needed to provide the circuit access required to achieve ultra-low defect levels at manufacturing and enable the detection of new failures later in the field. Updated standards for secure and effective test are also needed to ensure interoperability. This topic considers all hardware aspects of design for test for circuits and system architectures such as NoC, SoC, classical 2-D, 2.5-D and 3-D test and chiplets. We cover among others built-in self-test, scan design, test interfaces, and online monitoring, as well as all test and test access standards and their applications.
T5 – Test and Reliability for Analog, Mixed-Signal, and RF
Despite many years of research efforts, Analog, Mixed-Signal and RF test remains highly circuit-specific. The complexity of the problem stems from both the diversity of performance specifications and the sensitivity to any change in the signal path. However, AMS-RF researchers are undeterred, and this topic will bring together their latest advances. Topics include test and reliability in analogue and mixed-signal circuits, high-speed digital circuits, MEMS sensors and RF circuits.
T4 – Security and Trust
This topic includes methods, design solutions, and tools aimed at enhancing security and trust, with a particular focus on dependability issues encompassing test, reliability, and safety. More in particular, we consider papers targeting Test and Security (discussing security issues in test and the testing of secure devices), Fault Attacks and Countermeasures (fault-injection equipment, fault-based cryptanalysis, case studies), Dependability of Secure Circuits (including security primitives such as PUFs and TRNGs), Trust Issues and Countermeasures (hardware Trojans, reverse engineering, and supply chain attacks), Side Channel Analysis and Countermeasures (power attacks, timing attacks, microarchitectural attacks, covert channels).
T3 – Methods for Emerging Technologies and Architectures
Until now, incremental improvements in device technology and computer architecture make the development of high-performance applications possible. However, limitations on transistor miniaturization and today’s emerging applications requirements pose challenges with respect to CMOS technology scaling and von Neumann architecture. A paradigm shift is needed to enable new performance breakthroughs, such as non-CMOS-based technology as well as novel processing and computing paradigms, leading to new defect mechanisms, faulty behaviors and eventually novel DfT techniques. This topic considers aspects related to test and reliability for: emerging memories; in-memory computing; neuromorphic architectures; approximate circuits; photonic devices and architectures; quantum and reversible circuits and architectures.
T2 – Functional Safety, Fault Tolerance and Reliability
Functional safety (FuSa) and reliability are essential aspects of modern electronic systems, especially in automotive, aerospace, medical, and industrial domains. These systems require advanced design and test methods to ensure their correct, secure, and dependable operation in the field. Topics of interest include: dependability enforcement, defense mechanisms, design for reliability, safety insurance, fault detection or tolerance techniques, online testing, self-repair, robustness assessment methods, fault injection, and yield analysis.
T1 – Dependable AI and AI for Testing
AI/ML is thriving across numerous applications and we are only at the beginning of the revolution. Not surprisingly, AI/ML is gaining popularity for solving dependability and testing problems for ICs. In parallel, we need to address the problem of dependability and testing of emerging AI applications on hardware accelerators. This topic considers fault modeling, structural testing, functional testing, on-line test, reliability, fault tolerance and functional safety, all for AI/ML applications on hardware. Also, it considers the application of AI/ML in IC manufacturing testing, reliability, fault diagnosis and failure analysis, on-line testing, anomaly detection, and functional safety.
Venue
ETS 2027 will take place at Senate House, Bloomsbury, London.
Senate House, University of London
The symposium will be hosted in Bloomsbury, within walking distance of major London transport links, hotels, museums, restaurants and cultural venues.
Address: Senate House, Malet Street, London WC1E 7HU, United Kingdom.
Sponsors and Supporters
Corporate Support
Financial and Technical Sponsors
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